Current steering circuits are able to rapidly switch, or steer, the current output of a constant current source between an output leg and a ground leg, thereby switching the output current. A common application for such circuits is video DACs (D-to-A converters) that control the electron guns for video display tubes.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention can be applied: improving the performance of current steering circuits in terms of speed and/or accuracy.
FIG. 1 illustrates a portion of a conventional video DAC application using current steering. The DAC, including current steering circuitry, provides switched output current through a COAX connection to a video display tube for controlling an electron gun. The current steering circuitry is shown implemented in PMOS, although NMOS, CMOS and bipolar implementations have been used.
A current source PCS controlled by a compensated bias attempts to feed a constant current into a summing node SN. The current is steered into either an output leg or a ground leg by data switching logic DX coupled to the control gate of a transistor PDX in the ground leg, while a control or control voltage VREF is applied to the control gate of a transistor PREF in the output leg.
As PDX is switched by the DX signal (for example, at 150 MHz), causing PREF to switch at the same rate, the gate-to-source capacitance C.sub.GS of PDX results in AC coupling to the summing node SN. These capacitive effects cause voltage perturbations at SN, which in turn affects the gate-to-source voltage V.sub.GS of the current source PCS. For example, as DX switches HI, the capacitive effect of C.sub.GS tends to drive the summing node HI--because of the gate-to-drain capacitance C.sub.GD of PCS, this voltage perturbation at SN reduces the V.sub.GS of PCS, hence reducing current flow through PCS.
The increased noise at SN makes it difficult to maintain a constant current through PCS, even with a compensated bias, a condition which adversely affects performance. As a result, design trade-offs must be made regarding speed, accuracy, and glitch energy. Thus, to achieve greater switching speeds, on the order of 500 MHz, accuracy is generally limited to 4 bits, while providing 8 bit accuracy requires slower switching speeds, on the order of 150 MHz.
Accordingly, a need exists for a compensation scheme to counteract perturbations at the summing node of a current steering circuit, thereby allowing increased performance in terms of speed and accuracy.